FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

Vandana Thind; Bishwajeet Pandey; Kartik Kalia; Dil muhammed Akbar Hussain; Teerath Das; Tanesh Kumar

FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

Vandana Thind, Bishwajeet Pandey, Kartik Kalia, Dil muhammed Akbar Hussain, Teerath Das, Tanesh Kumar

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Publikation: Bidrag til tidsskrift › Konferenceartikel i tidsskrift › Forskning › peer review

8 Citationer (Scopus)

Abstract

In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.

Originalsprog	Engelsk
Tidsskrift	International Journal of Software Engineering and Its Application
Vol/bind	10
Udgave nummer	6
Sider (fra-til)	81-92
Antal sider	12
ISSN	1738-9984
Status	Udgivet - jun. 2016
Begivenhed	International Conference on Recent Trends in Computer Science and Electronics Engineering - Kuala Lumpur, Malaysia Varighed: 2 jan. 2016 → 3 jan. 2016

Konference

Konference	International Conference on Recent Trends in Computer Science and Electronics Engineering
Land/Område	Malaysia
By	Kuala Lumpur
Periode	02/01/2016 → 03/01/2016

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http://www.sersc.org/journals/IJSEIA/vol10_no6_2016/7.pdf

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Citationsformater

@inproceedings{e7648c222a834c7183257f7ea5877afc,

title = "FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology",

abstract = "In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.",

keywords = "DES Algorithm, IO standards, MOBILE_DDR, HSUL_12, LVTTL, LVCMOS, Power dissipation",

author = "Vandana Thind and Bishwajeet Pandey and Kartik Kalia and Hussain, {Dil muhammed Akbar} and Teerath Das and Tanesh Kumar",

year = "2016",

month = jun,

language = "English",

volume = "10",

pages = "81--92",

journal = "International Journal of Software Engineering and Its Application",

issn = "1738-9984",

publisher = "SERSC Science & Engineering Research Support Society",

number = "6",

note = "International Conference on Recent Trends in Computer Science and Electronics Engineering, RTCSE 2016 ; Conference date: 02-01-2016 Through 03-01-2016",

}

TY - GEN

T1 - FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

AU - Thind, Vandana

AU - Pandey, Bishwajeet

AU - Kalia, Kartik

AU - Hussain, Dil muhammed Akbar

AU - Das, Teerath

AU - Kumar, Tanesh

PY - 2016/6

Y1 - 2016/6

N2 - In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.

AB - In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.

KW - DES Algorithm

KW - IO standards

KW - MOBILE_DDR

KW - HSUL_12

KW - LVTTL

KW - LVCMOS

KW - Power dissipation

UR - http://rtcse.org/RTCSE_2016_Proceedings.pdf

UR - http://www.sersc.org/journals/IJSEIA/

M3 - Conference article in Journal

SN - 1738-9984

VL - 10

SP - 81

EP - 92

JO - International Journal of Software Engineering and Its Application

JF - International Journal of Software Engineering and Its Application

IS - 6

T2 - International Conference on Recent Trends in Computer Science and Electronics Engineering

Y2 - 2 January 2016 through 3 January 2016

ER -

FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

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