TY - JOUR
T1 - High Performance and Energy Efficient Traffic Light Controller Design Using FPGA
AU - Pandey, Sujeet
AU - Shrivastav, Vivek Kumar
AU - Sharma, Rashmi
AU - Hussain, Dil muhammed Akbar
PY - 2017/7
Y1 - 2017/7
N2 - In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER simulator.
AB - In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER simulator.
KW - Traffic Light Controller
KW - FPGA
KW - Verilog
KW - Energy Efficient Design
M3 - Journal article
SN - 2456-0065
VL - 3
SP - 9
EP - 16
JO - Gyancity Journal of Engineering and Technology
JF - Gyancity Journal of Engineering and Technology
IS - 2
ER -