Parallel Connection of Silicon Carbide MOSFETs for Multichip Power Modules

SiC technology has been under a rapid growth in the last decades, thanks to its wide band gap material superiorities, which leads to a higher breakdown voltage, a higher temperature limitation, a smaller thermal impedance and a faster switching speed of the SiC power devices compared to Si. Among the several kinds of SiC power devices, SiC MOSFET is considered to be the most promising to be commercialized and an alternative of Si IGBT, because of its unipolar device structure, voltage gate control and normally-off transistor property.

Along with the benefits of SiC MOSFETs, there are also some challenges from the manufacture and application points of view. The less mature manufacture process limits the yield and the single die size of the SiC MOSFETs, which results a smaller current capability of a single SiC MOSFET die. Consequently, in high current application, the paralleled connections of SiC MOSFET dies are required. In addition, the fast switching speed makes SiC MOSFETs more sensitive to the circuit parasitic parameters. The circuit parameters in the present Si IGBT power module packaging technology may be too critical for SiC MOSFETs.

This dissertation investigates the switching characterization of SiC MOSFETs regarding the influence of switching loop stray inductance and common source stray inductance. The pulse current measurement methods of fast switching speed power devices are summarized and a new method witch silicon steel current transformer is presented.

With the knowledge of the switching characterization of SiC MOSFETs, the paralleled connection of SiC MOSFETs is studied regarding both the influence of device mismatch and circuit mismatch. The circuit mismatches of switching loop stray inductance and common source stray inductance are first analyzed and experimentally investigated.

Then the DBC layout of a power module with paralleled SiC MOSFETs is presented and mathematically analyzed considering the influence of the circuit mismatch among the paralleled dies. It is revealed that there is a large common source stray inductance mismatch among the paralleled SiC MOSFETs, which leads to a significant transient current imbalance during the switching period. Besides the circuit mismatch, a current coupling effect is also found in the DBC layout, which aggravates the transient current imbalance among the paralleled SiC MOSFET dies. The discussions about the effects of the auxiliary source connections for the paralleled dies are presented and the source of the transient current imbalance is concluded.

To mitigate the transient current imbalance in the traditional DBC layout, a novel DBC layout with split output is proposed. First, the working mechanism of the split output topology is studied, which turns out to be able to improve the efficiency compared to the traditional half bridge. Besides the split output topology benefits, compared to the traditional DBC layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect, which consequently improves the current sharing performance among the paralleled SiC MOSFET dies in the power module. The proposed DBC layout is not only limited for SiC MOSFETs, but also for Si IGBTs and other voltage controlled devices.

of the circuit mismatch on the paralleled connection of SiC MOSFETs. It reveals the circuit mismatch and the current imbalance in the traditional DBC layout of power modules with paralleled dies. Based on that, a novel DBC layout for current imbalance mitigation is proposed. The more important point is that it starts the study of the DBC layout regarding the current distribution among the paralleled dies in the power module. The analysis method of the DBC layout provides new design guidelines and evaluation criteria of the DBC layout for multichip power modules with paralleled power semiconductor dies.