Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of the phase-locked loops (PLLs), which is of vital significance for the grid-integration and stable operation of power electronic converters to the electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques were proposed recently to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison among the advanced MAF-based PLL algorithms is presented, which includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various grid voltage disturbance scenarios, such as grid voltage sag, voltage flicker, and harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for HPLL under frequency jumps scenario is presented to compensate the steady-state error caused by the non-frequency adaptive DSC, and a satisfactory performance has been achieved.