Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three different level of voltage with 16 IO standards and we get three different power analysis for each IO Standards. IO power dissipation of FIR filter is 150mW with SSTL_18_II IO standard. When we migrate our design with HSTL_I, HSUL_12, LVCMOS15, LVTTL, MOBILE_DDR, and PCI33_3 IO standards then there is 53.33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family.