System and Circuit Design Aspects for CMOS Wireless Handset Receivers
Publikation: Forskning › PhD. afhandling
The presented work deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. First, an overview, from a historic perspective, on the use of CMOS in cellular applications is provided. Based on this the tremendous developments in CMOS technology are considered and the short-comings from an analog design perspective are evaluated. The lack of high quality passive devices, inductors in particular, is found to be one of the major obstacles in achieving a fully integrated RF design based on CMOS. Following this, an overview of different receiver architectures is given and a discussion of some fundamental problems in relation to CMOS integration is addressed. Based on the standards provided for Universal Mobile Telephone System (UMTS) a set of requirements is derived for a UTRA/FDD (UMTS Terrestial Radio Access - Frequency Division Duplex) direct-conversion receiver (DCR). The wideband nature of the UMTS signal opens up for simple DC-offset cancellation schemes. In line of this the use of highpass filtering as a means to reduce the DC-offset is pursued using link simulations. To simplify receiver planning it is common practice to employ a full separation of different distortion mechanisms. While this approach is very useful when an implementation performance surplus is available it is not an option when a low-cost silicon technology is the target. To manage this, a simple approach that allows all interfering components to be considered simultaneously is presented. Concerning the practical implementation of the DCR, LO leakage represents a significant source to performance degradation. Due to its antenna-like characteristics and typically large areas the inductor is especially prone to crosstalk and therefore a potential contributor to LO leakage. To minimize the coupling to and from inductors the traditional approach is to use guard-ring structures. While guard-rings improve isolation they also form a trade-off between device area and performance. The relation between guard-ring area and inductor performance is evaluated and it is shown that, depending on the size of the guard-ring, the Q-value reduction is found to be significantly reduced at RF frequencies. In continuation of this, various coupling effects for CMOS on-chip co-planar spiral inductors are presented. Simple guard-rings are shown to improve isolation between closely spaced adjacent inductors by approximately 10-15dB. At larger distances the gain of having a guard-ring reduces and eventually the gain reduces to zero dB. For modeling purposes an extended lumped element model is proposed and found to fit very well with crosstalk measurements.
|Udgiver||Department of Electronic Systems, Aalborg University|
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