Energy optimization for single- and heterogeneous multi-processor architectures, using Dynamic Voltage Scaling methods

The general trend today is towards mobility when talking systems in the area of mobile-communication, entertainment, and personal computing. Implementing such systems the battery capacity or energy consumption has become today's major design challenge. Invoking a need for design methodologies and methods for reducing the ever growing gap between battery capacity and the enlarging energy consumption of the more and more advanced portable embedded systems. These systems most often contain programmable processors, where this work focuses on evaluating energy reduction using the methodology of Dynamic Voltage Scaling (DVS). DVS is a performance scaling method where the processor voltage supply and clock frequency are scaled simultaneously, using software scheduling information. Hence the relation between processor performance and energy consumption is a quadratic function, DVS methods becomes an effective mean to reduce energy consumption - at least theoretically.
The contribution of this PhD project is an evaluation environment, where a model based approach is used to represent the processor architecture and application task-set. This approach enables a thorough evaluation, where processor - both single- and multi-processor architectures - and task-set specifications can be tested for its energy reducing capabilities