A Systematic Approach to Design High-Order Phase-Locked Loops

Saeed Golestan, Francisco Daniel Freijedo Fernandez, Josep M. Guerrero

Research output: Contribution to journalJournal articleResearchpeer-review

61 Citations (Scopus)
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Abstract

A basic approach to improve the performance of phase-locked loop (PLL) under adverse grid condition is to incorporate a first-order low-pass filter (LPF) into its control loop. The first-order LPF, however, has a limited ability to suppress grid disturbances. A natural thought to further improve the disturbance rejection capability of PLL is to use high order LPFs, resulting in high order PLLs. Application of high order LPFs, however, results in high order PLLs, which rather complicates the PLL analysis and design procedure. To overcome this challenge, a systematic method to design high order PLLs is presented in this letter. The suggested approach has a general theme, which means it can be applied to design the PLL control parameters regardless of the order of in-loop LPF. The effectiveness of suggested design method is confirmed through different design cases.
Original languageEnglish
JournalI E E E Transactions on Power Electronics
Volume30
Issue number6
Pages (from-to)2885 - 2890
Number of pages6
ISSN0885-8993
DOIs
Publication statusPublished - Jun 2015

Keywords

  • Phase-locked loop (PLL)
  • Synchronization

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