Abstract
The phase-locked loops (PLLs) are widely used in different areas of applications particularly for synchronization and control purposes in grid connected applications. A major challenge associated with the PLLs is how to improve their
dynamic performance without jeopardizing their stability and filtering capability. Recently, some approaches based on adding a secondary control path (SCP) to the PLL structure have been proposed to deal with this challenge. The objective of this letter is to briefly analyze these approaches. The study starts with an overview of the PLLs with SCP. The letter proceeds with the small-signal modeling of some of these PLLs, which significantly simplifies the analysis. Using these models, the effects of adding the SCP on the PLL structure are studied. The obtained results show that the SCP may not be a practical approach to improve
the PLL dynamic performance as it aggravates the stability problem.
dynamic performance without jeopardizing their stability and filtering capability. Recently, some approaches based on adding a secondary control path (SCP) to the PLL structure have been proposed to deal with this challenge. The objective of this letter is to briefly analyze these approaches. The study starts with an overview of the PLLs with SCP. The letter proceeds with the small-signal modeling of some of these PLLs, which significantly simplifies the analysis. Using these models, the effects of adding the SCP on the PLL structure are studied. The obtained results show that the SCP may not be a practical approach to improve
the PLL dynamic performance as it aggravates the stability problem.
| Original language | English |
|---|---|
| Journal | I E E E Transactions on Industrial Electronics |
| Volume | 61 |
| Issue number | 9 |
| Pages (from-to) | 4824-4828 |
| Number of pages | 5 |
| ISSN | 0278-0046 |
| DOIs | |
| Publication status | Published - 2014 |
Keywords
- Dynamic performance
- Phase locked loop (PLL)
- Synchronization.