Abstract
We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.
Original language | English |
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Title of host publication | Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015 |
Number of pages | 5 |
Publisher | IEEE Press |
Publication date | 2015 |
Pages | 1-5 |
ISBN (Electronic) | 978-1-4673-6576-5 |
DOIs | |
Publication status | Published - 2015 |
Event | Nordic Circuits and Systems Conference (NORCAS) - Oslo, Norway Duration: 26 Oct 2015 → 28 Oct 2015 |
Conference
Conference | Nordic Circuits and Systems Conference (NORCAS) |
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Location | Oslo |
Country/Territory | Norway |
Period | 26/10/2015 → 28/10/2015 |