Abstract
Convolution encoder and Viterbi decoder are the basic and important blocks in any Code Division Multiple Accesses (CDMA). They are widely used in communication system due to their error correcting capability But the performance degrades with variable constraint length. In this context to have detailed analysis, this paper deals with the implementation of convolution encoder and Viterbi decoder using system on programming chip (SOPC). It uses variable constraint length of 7, 8 and 9 bits for 1/2 and 1/3 code rates. By analyzing the Viterbi algorithm it is seen that our algorithm has a better error rate for ½ code rates than 1/3. The reduced bit error rate with increasing constraint length shows an increase in efficiency and better utilization of resources as bandwidth and power.
| Original language | English |
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| Title of host publication | 2013 IEEE 3rd International Advance Computing Conference (IACC) : IACC2013 |
| Place of Publication | AKGEC, Ghaziabad, INDIA |
| Publisher | IEEE |
| Publication date | 23 Feb 2013 |
| Pages | 1651-1655 |
| ISBN (Print) | 978-1-4673-4527-9 |
| DOIs | |
| Publication status | Published - 23 Feb 2013 |
| Event | 3rd IEEE International Advance Computing Conference (IACC-2013) - Ghaziabad , India Duration: 22 Feb 2013 → 23 Feb 2013 |
Conference
| Conference | 3rd IEEE International Advance Computing Conference (IACC-2013) |
|---|---|
| Country/Territory | India |
| City | Ghaziabad |
| Period | 22/02/2013 → 23/02/2013 |
Keywords
- Convolution encoder; Viterbi decoder; SOPC; constraint length;