DC-Offset Rejection in Phase-Locked Loops: A Novel Approach

Saeed Golestan; Josep M. Guerrero; Juan C. Vasquez

doi:10.1109/TIE.2016.2546219

DC-Offset Rejection in Phase-Locked Loops: A Novel Approach

Saeed Golestan, Josep M. Guerrero, Juan C. Vasquez

AAU Energy

Research output: Contribution to journal › Journal article › Research › peer-review

49 Citations (Scopus)

Abstract

Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in power and energy applications. A challenging problem in designing PLLs is the presence of DC offset in their input, which causes fundamental frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.

Original language	English
Article number	7439853
Journal	IEEE Transactions on Industrial Electronics
Volume	63
Issue number	8
Pages (from-to)	4942-4946
Number of pages	5
ISSN	0278-0046
DOIs	https://doi.org/10.1109/TIE.2016.2546219
Publication status	Published - Aug 2016

Keywords

Phase locked loops
Synchronisation

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10.1109/TIE.2016.2546219

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title = "DC-Offset Rejection in Phase-Locked Loops: A Novel Approach",

abstract = "Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in power and energy applications. A challenging problem in designing PLLs is the presence of DC offset in their input, which causes fundamental frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.",

keywords = "Phase locked loops, Synchronisation",

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year = "2016",

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T2 - A Novel Approach

AU - Golestan, Saeed

AU - Guerrero, Josep M.

AU - Vasquez, Juan C.

PY - 2016/8

Y1 - 2016/8

N2 - Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in power and energy applications. A challenging problem in designing PLLs is the presence of DC offset in their input, which causes fundamental frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.

AB - Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in power and energy applications. A challenging problem in designing PLLs is the presence of DC offset in their input, which causes fundamental frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.

KW - Phase locked loops

KW - Synchronisation

U2 - 10.1109/TIE.2016.2546219

DO - 10.1109/TIE.2016.2546219

M3 - Journal article

AN - SCOPUS:84978630527

SN - 0278-0046

VL - 63

SP - 4942

EP - 4946

JO - IEEE Transactions on Industrial Electronics

JF - IEEE Transactions on Industrial Electronics

IS - 8

M1 - 7439853

ER -

DC-Offset Rejection in Phase-Locked Loops: A Novel Approach

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Keywords

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