TY - JOUR

T1 - Design and Tuning of a Modified Power-Based PLL for Single-Phase Grid-Connected Power Conditioning Systems

A1 - Golestan,Saeed

A1 - Monfared,Mohammad

A1 - D. Freijedo,Francisco

A1 - Guerrero,Josep M.

AU - Golestan,Saeed

AU - Monfared,Mohammad

AU - D. Freijedo,Francisco

AU - Guerrero,Josep M.

PB - I E E E

PY - 2012

Y1 - 2012

N2 - One of the most important aspects for the proper operation of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchronization techniques, phase locked loop (PLL) based algorithms have found a lot of interest for the advantages they present. Typically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double frequency oscillations which appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evaluated through a detailed mathematical analysis. A systematic design method to fine-tune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effectiveness of the proposed PLL.

AB - One of the most important aspects for the proper operation of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchronization techniques, phase locked loop (PLL) based algorithms have found a lot of interest for the advantages they present. Typically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double frequency oscillations which appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evaluated through a detailed mathematical analysis. A systematic design method to fine-tune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effectiveness of the proposed PLL.

KW - Frequency estimation

KW - Phase estimation

KW - Phase-locked loop (PLL)

KW - Power-based PLL (pPLL)

KW - Synchronization

KW - Single phase grid-connected converters

U2 - 10.1109/TPEL.2012.2183894

DO - 10.1109/TPEL.2012.2183894

JO - I E E E Transactions on Power Electronics

JF - I E E E Transactions on Power Electronics

SN - 0885-8993

IS - 8

VL - 27

SP - 3639

EP - 3650

ER -