Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules

Amir Sajjad Bahman; Frede Blaabjerg; Atanu Dutta; Alan Mantooth

doi:10.1109/APEC.2016.7468292

Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules

Amir Sajjad Bahman, Frede Blaabjerg, Atanu Dutta, Alan Mantooth

AAU Energy

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

21 Citations (Scopus)

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Abstract

The reliability of power modules is closely depended on their electrical and thermal behavior in operation. As power modules are built to operate more integrated and faster, the electrical parasitic and thermal stress issues become more critical. This paper investigates simplified thermal and parasitic inductance models of SiC power modules. These models can replace the models by Finite Element Methods (FEM) to predict temperatures and electrical parasitics of power modules with much faster speed and acceptable errors and will be used for study of real operation of power modules. As a case study, the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by
FEM simulations and also experiment.

Original language	English
Title of host publication	Proceedings of the 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
Number of pages	8
Publisher	IEEE
Publication date	Mar 2016
Pages	3012 - 3019
ISBN (Print)	978-1-4673-8393-6, 978-1-4673-9551-9
ISBN (Electronic)	978-1-4673-9550-2
DOIs	https://doi.org/10.1109/APEC.2016.7468292
Publication status	Published - Mar 2016
Event	2016 IEEE Applied Power Electronics Conference and Exposition (APEC) - Long Beach Convention and Entertainment Center, Long Beach, United States Duration: 20 Mar 2016 → 24 Mar 2016 http://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=32616

Conference

Conference	2016 IEEE Applied Power Electronics Conference and Exposition (APEC)
Location	Long Beach Convention and Entertainment Center
Country/Territory	United States
City	Long Beach
Period	20/03/2016 → 24/03/2016
Internet address	http://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=32616

Keywords

Electrical parasitic modeling
Thermal modeling
SiC power module
Optimization
Reliability

Access to Document

10.1109/APEC.2016.7468292

Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC ModulesAccepted author manuscript, 1.22 MB

AUB Link

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Center Of Reliable Power Electronics (CORPE)
Blaabjerg, F., Munk-Nielsen, S., Pedersen, K. & Popok, V.
01/04/2011 → 31/12/2016
Project: Research

Cite this

@inproceedings{a7dd1efbcfc1434d87d13990bbea4b69,

title = "Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules",

abstract = "The reliability of power modules is closely depended on their electrical and thermal behavior in operation. As power modules are built to operate more integrated and faster, the electrical parasitic and thermal stress issues become more critical. This paper investigates simplified thermal and parasitic inductance models of SiC power modules. These models can replace the models by Finite Element Methods (FEM) to predict temperatures and electrical parasitics of power modules with much faster speed and acceptable errors and will be used for study of real operation of power modules. As a case study, the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by FEM simulations and also experiment. ",

keywords = "Electrical parasitic modeling, Thermal modeling, SiC power module, Optimization, Reliability",

author = "Bahman, {Amir Sajjad} and Frede Blaabjerg and Atanu Dutta and Alan Mantooth",

year = "2016",

month = mar,

doi = "10.1109/APEC.2016.7468292",

language = "English",

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booktitle = "Proceedings of the 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC)",

publisher = "IEEE",

address = "United States",

note = "2016 IEEE Applied Power Electronics Conference and Exposition (APEC) ; Conference date: 20-03-2016 Through 24-03-2016",

url = "http://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=32616",

}

Bahman, AS , Blaabjerg, F, Dutta, A & Mantooth, A 2016, Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules. in Proceedings of the 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, pp. 3012 - 3019, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, United States, 20/03/2016. https://doi.org/10.1109/APEC.2016.7468292

Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules. / Bahman, Amir Sajjad ; Blaabjerg, Frede; Dutta, Atanu et al.
Proceedings of the 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2016. p. 3012 - 3019.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules

AU - Bahman, Amir Sajjad

AU - Blaabjerg, Frede

AU - Dutta, Atanu

AU - Mantooth, Alan

PY - 2016/3

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N2 - The reliability of power modules is closely depended on their electrical and thermal behavior in operation. As power modules are built to operate more integrated and faster, the electrical parasitic and thermal stress issues become more critical. This paper investigates simplified thermal and parasitic inductance models of SiC power modules. These models can replace the models by Finite Element Methods (FEM) to predict temperatures and electrical parasitics of power modules with much faster speed and acceptable errors and will be used for study of real operation of power modules. As a case study, the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by FEM simulations and also experiment.

AB - The reliability of power modules is closely depended on their electrical and thermal behavior in operation. As power modules are built to operate more integrated and faster, the electrical parasitic and thermal stress issues become more critical. This paper investigates simplified thermal and parasitic inductance models of SiC power modules. These models can replace the models by Finite Element Methods (FEM) to predict temperatures and electrical parasitics of power modules with much faster speed and acceptable errors and will be used for study of real operation of power modules. As a case study, the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by FEM simulations and also experiment.

KW - Electrical parasitic modeling

KW - Thermal modeling

KW - SiC power module

KW - Optimization

KW - Reliability

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DO - 10.1109/APEC.2016.7468292

M3 - Article in proceeding

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SN - 978-1-4673-9551-9

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EP - 3019

BT - Proceedings of the 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC)

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Y2 - 20 March 2016 through 24 March 2016

ER -

Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules

Abstract

Conference

Keywords

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Projects

Center Of Reliable Power Electronics (CORPE)

Cite this