Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature

Paula Diaz Reigosa; Francesco Iannuzzo; Lorenzo Ceccarelli

doi:10.1109/IPFA.2018.8452575

Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature

Paula Diaz Reigosa, Francesco Iannuzzo, Lorenzo Ceccarelli

The Faculty of Engineering and Science

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

11 Citations (Scopus)

585 Downloads (Pure)

Abstract

This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

Original language	English
Title of host publication	Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Number of pages	5
Volume	2018-July
Publisher	IEEE Press
Publication date	Jul 2018
Pages	1-5
Article number	8452575
ISBN (Print)	978-1-5386-4930-5
ISBN (Electronic)	978-1-5386-4929-9
DOIs	https://doi.org/10.1109/IPFA.2018.8452575
Publication status	Published - Jul 2018
Event	25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018 - Singapore, Singapore Duration: 16 Jul 2018 → 19 Jul 2018

Conference

Conference	25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018
Country/Territory	Singapore
City	Singapore
Period	16/07/2018 → 19/07/2018
Sponsor	Hamamatsu Photonics K.K., Thermo Fisher Scientific, Inc.

Series	IEEE International Symposium on Physical & Failure Analysis of Integrated Circuit (IPFA)
ISSN	1946-1550

Keywords

Logic gates
Silicon carbide
MOSFET
Failure analysis
Leakage currents
Ion beams
Aluminum

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10.1109/IPFA.2018.8452575

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Cite this

Reigosa, Paula Diaz ; Iannuzzo, Francesco ; Ceccarelli, Lorenzo. / Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Vol. 2018-July IEEE Press, 2018. pp. 1-5 (IEEE International Symposium on Physical & Failure Analysis of Integrated Circuit (IPFA)).

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title = "Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature",

abstract = "This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.",

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author = "Reigosa, {Paula Diaz} and Francesco Iannuzzo and Lorenzo Ceccarelli",

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booktitle = "Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits",

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Reigosa, PD, Iannuzzo, F & Ceccarelli, L 2018, Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. in Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. vol. 2018-July, 8452575, IEEE Press, IEEE International Symposium on Physical & Failure Analysis of Integrated Circuit (IPFA), pp. 1-5, 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018, Singapore, Singapore, 16/07/2018. https://doi.org/10.1109/IPFA.2018.8452575

Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. / Reigosa, Paula Diaz; Iannuzzo, Francesco; Ceccarelli, Lorenzo.
Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Vol. 2018-July IEEE Press, 2018. p. 1-5 8452575 (IEEE International Symposium on Physical & Failure Analysis of Integrated Circuit (IPFA)).

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

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N2 - This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

AB - This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

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Reigosa PD, Iannuzzo F, Ceccarelli L. Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. In Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Vol. 2018-July. IEEE Press. 2018. p. 1-5. 8452575. (IEEE International Symposium on Physical & Failure Analysis of Integrated Circuit (IPFA)). doi: 10.1109/IPFA.2018.8452575

Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature

Abstract

Conference

Keywords

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Center Of Reliable Power Electronics (CORPE)

Cite this

Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature

Abstract

Conference

Keywords

Access to Document

AUB Link

Other files and links

Fingerprint

Projects

Center Of Reliable Power Electronics (CORPE)

Cite this