TY - JOUR
T1 - Reduced switch-count structure for symmetric multilevel inverters with a novel switched-DC-source submodule
AU - Avanaki, Hossein Nasiri
AU - Barzegarkhoo, Reza
AU - Zamiri, Elyas
AU - Yang, Yongheng
AU - Blaabjerg, Frede
PY - 2019/2/20
Y1 - 2019/2/20
N2 - The aim of this study is to present a new cost effective topology for Symmetric multilevel inverters (SMLIs) configurations, which can generate a great number of output voltage levels with a least of switching devices. The proposed structure contains a novel switched-dc-source (SDCS) sub-module that can produce three positive output voltage levels with a contribution of four equal dc voltage sources, two unidirectional, and one bi-directional power switches. Accordingly, to create a uniform staircase output voltage with multiple levels, the proposed SDCS sub-module is integrated into a new design. Therefore, a new family of reduced switch-count (RSC)-SMLIs is derived, which is capable of generating at least 13- and 15-level output voltages using only ten power switches and nine gate drivers. Furthermore, when employing several of the proposed SDCS sub-modules in series, a new generalised RSC-SMLI topology is obtained. Comparisons with prior-art SMLIs structures are done, which also highlights the beneficial potential of the proposed topology. To demonstrate the superior performance of the proposed topology, several simulation and experimental results have been provided.
AB - The aim of this study is to present a new cost effective topology for Symmetric multilevel inverters (SMLIs) configurations, which can generate a great number of output voltage levels with a least of switching devices. The proposed structure contains a novel switched-dc-source (SDCS) sub-module that can produce three positive output voltage levels with a contribution of four equal dc voltage sources, two unidirectional, and one bi-directional power switches. Accordingly, to create a uniform staircase output voltage with multiple levels, the proposed SDCS sub-module is integrated into a new design. Therefore, a new family of reduced switch-count (RSC)-SMLIs is derived, which is capable of generating at least 13- and 15-level output voltages using only ten power switches and nine gate drivers. Furthermore, when employing several of the proposed SDCS sub-modules in series, a new generalised RSC-SMLI topology is obtained. Comparisons with prior-art SMLIs structures are done, which also highlights the beneficial potential of the proposed topology. To demonstrate the superior performance of the proposed topology, several simulation and experimental results have been provided.
UR - http://www.scopus.com/inward/record.url?scp=85061340468&partnerID=8YFLogxK
U2 - 10.1049/iet-pel.2018.5089
DO - 10.1049/iet-pel.2018.5089
M3 - Journal article
SN - 1755-4535
VL - 12
SP - 311
EP - 321
JO - IET Power Electronics
JF - IET Power Electronics
IS - 2
ER -