Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

Nisha Pandey; Bishwajeet Pandey; Dil muhammed Akbar Hussain

doi:10.1109/SASG.2017.8356479

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

Nisha Pandey, Bishwajeet Pandey, Dil muhammed Akbar Hussain

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

1 Citation (Scopus)

254 Downloads (Pure)

Abstract

In Today’s World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.

Original language	English
Title of host publication	Proceedings of IEEE Saudi Arabia Smart Grid Conference (SASG 2017)
Number of pages	7
Publisher	IEEE Press
Publication date	Dec 2017
ISBN (Print)	978-1-5386-1877-6
ISBN (Electronic)	978-1-5386-1876-9
DOIs	https://doi.org/10.1109/SASG.2017.8356479
Publication status	Published - Dec 2017
Event	IEEE Saudi Arabia Smart Grid Conference (SASG 2017) - Jeddah, Saudi Arabia Duration: 12 Dec 2017 → 14 Dec 2017

Conference

Conference	IEEE Saudi Arabia Smart Grid Conference (SASG 2017)
Country/Territory	Saudi Arabia
City	Jeddah
Period	12/12/2017 → 14/12/2017

Keywords

Data Transmission
Networking
Packet Counter
Frequency Scaling
FPGA
Efficient

Access to Document

10.1109/SASG.2017.8356479

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency ScalingAccepted author manuscript, 382 KB

AUB Link

Search for the material in Aalborg University Library's search engine

Cite this

@inproceedings{32097eccbc5c41cda9005b28d32eeacc,

title = "Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling",

abstract = "In Today{\textquoteright}s World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.",

keywords = "Data Transmission, Networking, Packet Counter, Frequency Scaling, FPGA, Efficient",

author = "Nisha Pandey and Bishwajeet Pandey and Hussain, {Dil muhammed Akbar}",

year = "2017",

month = dec,

doi = "10.1109/SASG.2017.8356479",

language = "English",

isbn = "978-1-5386-1877-6",

booktitle = "Proceedings of IEEE Saudi Arabia Smart Grid Conference (SASG 2017)",

publisher = "IEEE Press",

note = "IEEE Saudi Arabia Smart Grid Conference (SASG 2017) ; Conference date: 12-12-2017 Through 14-12-2017",

}

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling. / Pandey, Nisha; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar.
Proceedings of IEEE Saudi Arabia Smart Grid Conference (SASG 2017). IEEE Press, 2017.

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

AU - Pandey, Nisha

AU - Pandey, Bishwajeet

AU - Hussain, Dil muhammed Akbar

PY - 2017/12

Y1 - 2017/12

N2 - In Today’s World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.

AB - In Today’s World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.

KW - Data Transmission

KW - Networking

KW - Packet Counter

KW - Frequency Scaling

KW - FPGA

KW - Efficient

U2 - 10.1109/SASG.2017.8356479

DO - 10.1109/SASG.2017.8356479

M3 - Article in proceeding

SN - 978-1-5386-1877-6

BT - Proceedings of IEEE Saudi Arabia Smart Grid Conference (SASG 2017)

PB - IEEE Press

T2 - IEEE Saudi Arabia Smart Grid Conference (SASG 2017)

Y2 - 12 December 2017 through 14 December 2017

ER -

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

Abstract

Conference

Keywords

Access to Document

AUB Link

Fingerprint

Cite this