Small-Signal Modeling, Stability Analysis and Design Optimization of Single-Phase Delay-Based PLLs

Generally speaking, designing single-phase phaselocked loops (PLLs) is more complicated than three-phase ones, as their implementation often involves the generation of a fictitious orthogonal signal for the frame transformation. In recent years, many approaches to generate the orthogonal signal have been proposed, the simplest perhaps being the transfer delay based method. In the transfer delay based PLL (TD-PLL), the orthogonal signal is generated by delaying the original singlephase signal by T=4 (one-quarter of a period). The phase shift caused by the transfer delay block, however, will not be exactly 90 under off-nominal grid frequencies, which results in errors in the estimated quantities by the TD-PLL. To alleviate this issue, an improved version of TD-PLL, called the non-frequency dependent TD-PLL (NTD-PLL), has recently been proposed. The NTD-PLL uses another T=4 delay unit in its feedback path to make the PLL immune to grid frequency variations. To the best of the authors’ knowledge, the accurate small-signal modeling of the TD-PLL and NTD-PLL has not yet been carried out, and no detailed analysis of their performance has been presented. The main aim of this paper is to address these issues and explore new methods to enhance their performance. The stability analysis, control design guidelines and performance comparison with the state-of-the-art PLLs are presented as well.