Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

Vandana Thind; Sujeet Pandey; Dil muhammed Akbar Hussain; Bhagwan Das; M F L Abdullah; Bishwajeet Pandey

doi:10.1007/978-981-10-8533-8_13

Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

Vandana Thind, Sujeet Pandey, Dil muhammed Akbar Hussain, Bhagwan Das, M F L Abdullah, Bishwajeet Pandey

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

2 Citations (Scopus)

Abstract

In this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path. The cases on which analysis is done are like worst case slack, best case achievable, timing error and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis there is maximum of 19.56% of variation in worst case slack, 0.29% change for best case achievable, 41.17% change in timing error and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signal, accordingly we have design our own algorithm with strong security encryption.

Original language	English
Title of host publication	System and Architecture - Proceedings of CSI 2015
Editors	Sunil Kumar Muttoo
Number of pages	15
Publisher	Springer
Publication date	May 2018
Pages	123-137
ISBN (Print)	9789811085321
DOIs	https://doi.org/10.1007/978-981-10-8533-8_13
Publication status	Published - May 2018
Event	50th Golden Jubilee Annual Convention of Computer Society of India - New Delhi, India Duration: 2 Dec 2015 → 5 Dec 2015 Conference number: 50 http://www.csi-2015.org/

Conference

Conference	50th Golden Jubilee Annual Convention of Computer Society of India
Number	50
Country/Territory	India
City	New Delhi
Period	02/12/2015 → 05/12/2015
Internet address	http://www.csi-2015.org/

Series	Advances in Intelligent Systems and Computing
Volume	732
ISSN	2194-5357

Keywords

Timing constraints
DES algorithm
28-nm FPGA
Pin-out report
Mapping report
Minimum period
Maximum performance
Static timing analysis

Access to Document

10.1007/978-981-10-8533-8_13

AUB Link

Search for the material in Aalborg University Library's search engine

Cite this

@inproceedings{77e02e67475f4c9381a69876246e2d10,

title = "Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA",

abstract = "In this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path. The cases on which analysis is done are like worst case slack, best case achievable, timing error and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis there is maximum of 19.56% of variation in worst case slack, 0.29% change for best case achievable, 41.17% change in timing error and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signal, accordingly we have design our own algorithm with strong security encryption.",

keywords = "Timing constraints, DES algorithm, 28-nm FPGA, Pin-out report, Mapping report, Minimum period, Maximum performance, Static timing analysis",

author = "Vandana Thind and Sujeet Pandey and Hussain, {Dil muhammed Akbar} and Bhagwan Das and Abdullah, {M F L} and Bishwajeet Pandey",

year = "2018",

month = may,

doi = "10.1007/978-981-10-8533-8_13",

language = "English",

isbn = "9789811085321",

series = "Advances in Intelligent Systems and Computing",

publisher = "Springer",

pages = "123--137",

editor = "Muttoo, {Sunil Kumar}",

booktitle = "System and Architecture - Proceedings of CSI 2015",

address = "Germany",

note = "50th Golden Jubilee Annual Convention of Computer Society of India, CSI 2015 ; Conference date: 02-12-2015 Through 05-12-2015",

url = "http://www.csi-2015.org/",

}

Thind, V, Pandey, S, Hussain, DMA, Das, B, Abdullah, MFL & Pandey, B 2018, Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA. in SK Muttoo (ed.), System and Architecture - Proceedings of CSI 2015. Springer, Advances in Intelligent Systems and Computing, vol. 732, pp. 123-137, 50th Golden Jubilee Annual Convention of Computer Society of India, New Delhi, India, 02/12/2015. https://doi.org/10.1007/978-981-10-8533-8_13

Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA. / Thind, Vandana; Pandey, Sujeet; Hussain, Dil muhammed Akbar et al.
System and Architecture - Proceedings of CSI 2015. ed. / Sunil Kumar Muttoo. Springer, 2018. p. 123-137 (Advances in Intelligent Systems and Computing, Vol. 732).

Research output: Contribution to book/anthology/report/conference proceeding › Article in proceeding › Research › peer-review

TY - GEN

T1 - Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

AU - Thind, Vandana

AU - Pandey, Sujeet

AU - Hussain, Dil muhammed Akbar

AU - Das, Bhagwan

AU - Abdullah, M F L

AU - Pandey, Bishwajeet

N1 - Conference code: 50

PY - 2018/5

Y1 - 2018/5

N2 - In this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path. The cases on which analysis is done are like worst case slack, best case achievable, timing error and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis there is maximum of 19.56% of variation in worst case slack, 0.29% change for best case achievable, 41.17% change in timing error and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signal, accordingly we have design our own algorithm with strong security encryption.

AB - In this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path. The cases on which analysis is done are like worst case slack, best case achievable, timing error and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis there is maximum of 19.56% of variation in worst case slack, 0.29% change for best case achievable, 41.17% change in timing error and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signal, accordingly we have design our own algorithm with strong security encryption.

KW - Timing constraints

KW - DES algorithm

KW - 28-nm FPGA

KW - Pin-out report

KW - Mapping report

KW - Minimum period

KW - Maximum performance

KW - Static timing analysis

UR - http://www.scopus.com/inward/record.url?scp=85047975653&partnerID=8YFLogxK

U2 - 10.1007/978-981-10-8533-8_13

DO - 10.1007/978-981-10-8533-8_13

M3 - Article in proceeding

SN - 9789811085321

T3 - Advances in Intelligent Systems and Computing

SP - 123

EP - 137

BT - System and Architecture - Proceedings of CSI 2015

A2 - Muttoo, Sunil Kumar

PB - Springer

T2 - 50th Golden Jubilee Annual Convention of Computer Society of India

Y2 - 2 December 2015 through 5 December 2015

ER -

Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

Abstract

Conference

Keywords

Access to Document

AUB Link

Other files and links

Fingerprint

Cite this