A UTRA/FDD Receiver Architecture and LNA in CMOS Technology



The purpose of this Industrial PhD project was to study receiver architectures and RF-CMOS circuit technology for a UTRA/FDD (UMTS) handset receiver. Based on an investigation of the signal properties, the system requirements and potential for integration a direct conversion receiver architecture was chosen. It was shown that the well-known problem of distortion by varying envelope blocking signals (e.g. transmitter leakage) combined with even order non-linearities can be overcome by proper choice of architecture and block requirements. Accurate component modelling is mandatory for a successful RF-circuit design. One of the commonly used non-linear MOS-models, "MOS Model 9", has been shown to be inadequate for RF-design and has been extended. An excellent agreement between the extended model and measured RF-parameters was obtained in varying bias conditions. Also a "lateral flux" MIM-capacitor with low loss and high capacitance/area-ratio has been introduced. Two experimental LNA designs are made, both based on an inductively degenerated common source stage. One of the designs includes a gain switching circuit for use in AGC control. Simulation results and on-wafer measurements show good agreement. Some disagreement between simulation results and measurements on a PCB-mounted die indicates that the modelling of the coupling between bond wires needs to be improved. The measured noise figure, 3rd order intercept point and compression level are among the very best of published results. Christian Rye Iversen, Torben Larsen; Pia Thomsen, Siemens Mobile Phones)
Effektiv start/slut dato31/12/200331/12/2003