RF Front-end Technology to Telecommunications Equipment



Background and problem This project is a co-operation between The RF Integrated Systems and Circuits Group, Siemens Mobile Phones, RTX Telecom, Texas Instruments, Telital, and Maxon Telecom. The purpose of this joint research project is to establish a set of radio receiver requirements for the coming third-generation wireless communications standard that is to be based on wideband CDMA (WCDMA). Further, the purpose is to design, implement, and to test a receiver front-end capable off meeting these specifications. To limit the scope of the project the effort is aimed at the UTRA-FDD part of the UMTS standard. Furthermore, all implemented circuits are to be based on a standard sub-micron CMOS process. Based on an analysis of the test signal scenarios specified in the standard, system requirements are derived for generic receiver architecture. It is shown that the simultaneous transmission and reception presents the harshest receiver linearity requirement. The cause to this is the well-known problem of having varying envelope-blocking signals, such as the uplink transmitter signal, in an environment where even order non-linearity are present. In a worst-case scenario the even-order distortion output component of a receiver (and hence the input to the data receiver) is a composite signal containing both static and time-variant offsets - see CPK Annual Report 2001 - Figure 4.6.1a (Worst-case effect resulting from even-order distortion and examples of different high pass filter options). The transmitter leakage problem can be overcome by proper choice of architecture and through careful receiver planning. Based on detailed data receiver link simulations it has been shown how robust the W-CDMA signal is towards time-variant offset levels and to what extent high pass filtering may be utilized to mitigate the former [Mikkelsen et. al, NorChip99] - see CPK Annual Report 2001 - Figure 4.6.1a (Worst-case effect resulting from even-order distortion and examples of different highpass filter options). Based on these findings a cost-analysis (with CMOS block requirements as the driving parameter) leads to an optimised receiver, based on a combination of off-the-shelf discrete components and CMOS RF circuit blocks, where requirements towards both discrete and CMOS blocks are realistic. It is found that a servo-type feedback loop may be used to remove a majority of the offset resulting from RF signal processing while also serving to stabilize the DC levels of the base band signal processing blocks. This is then combined with an interstage band pass filter whereby overall receiver requirements are meet. In doing this a method for analysing receiver chains consisting of both power and voltage matched blocks is derived. The design methodology shown in CPK Annual Report 2001 - Figure 4.6.1b (Design methodology utilized to attain accurate receiver planning) was used for accurate receiver planning at the system level. The detailed receiver planning forms an optimum trade-off between noise and non-linear distortion in cascaded stages while including block selectivity. The resulting receiver shown in CPK Annual Report 2001 - Figure 4.6.1c (Resulting receiver architecture. An optimum trade-off is obtained using both discrete and CMOS blocks) is a direct-conversion type based on both discrete components and circuits implemented in CMOS. With the overall requirements fixed it is decided to use an on-chip single-ended to differential conversion based on a modified Gilbert-Cell mixer where the differential input stage is exited using only one input. The resulting layout shown in CPK Annual Report 2001 - Figure 4.6.1d (The resulting layout of the CMOS direct conversion receiver for UTRA-FDD) has been fabricated and the resulting CMOS chip is currently being measured. The work is by now completed. Jan Hvolgaard Mikkelsen, Michael Bohl Jenner, Ole Kiel Jensen, Ragnar Vidir Reynisson, Torben Larsen; Jørgen Bøjer, Morten Gentsch, Siemens Mobile Phones)
Effektiv start/slut dato31/12/200331/12/2003