Statistics-Based Layout Design Tool for Paralleled Semiconductors (STABLE)

We aim to develop a statistics-based design tool to predict the current and power loss distribution in multi-chip power modules when faced with a realistic distribution of semiconductor parameters. The tool will output a probability distribution of the likely imbalances between the chips in a substantially faster assessment than existing SPICE/Monte-Carlo based approaches.
The project is interdisciplinary combining mathematical probability and statistics methods with engineering and physics involved in pwoer electronics packaging. We hope to reduce the design time for power modules containing paralleled semiconductor chips but also expect the results to be usefull on a broader scope.