A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

G. Fikos, Lazaros Nalpantidis, S. Siskos

    Publikation: Bidrag til bog/antologi/rapport/konference proceedingBidrag til bog/antologiForskningpeer review

    1 Citation (Scopus)
    OriginalsprogEngelsk
    TitelIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
    Antal sider5
    Vol/bind2005
    Publikationsdato1 jan. 2005
    Sider199-203
    ISBN (Trykt)0780393341, 978-078039334-9
    DOI
    StatusUdgivet - 1 jan. 2005

    Fingerprint

    Photoelectric cells
    Noise abatement
    Amplification
    Capacitors
    Data storage equipment
    Networks (circuits)

    Emneord

    • Capacitors; CMOS integrated circuits; Noise abatement; Photoelectric cells; Control gate capacitors; Fixed Pattern Noise (FPN); Floating-gate mosfets (FGMOS); Logarithmic response photoarrays; MOS devices

    Citer dette

    Fikos, G., Nalpantidis, L., & Siskos, S. (2005). A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction. I IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (Bind 2005, s. 199-203) https://doi.org/10.1109/SIPS.2005.1579864
    Fikos, G. ; Nalpantidis, Lazaros ; Siskos, S. / A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Bind 2005 2005. s. 199-203
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    keywords = "Capacitors; CMOS integrated circuits; Noise abatement; Photoelectric cells; Control gate capacitors; Fixed Pattern Noise (FPN); Floating-gate mosfets (FGMOS); Logarithmic response photoarrays; MOS devices",
    author = "G. Fikos and Lazaros Nalpantidis and S. Siskos",
    year = "2005",
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    doi = "10.1109/SIPS.2005.1579864",
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    Fikos, G, Nalpantidis, L & Siskos, S 2005, A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction. i IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. bind 2005, s. 199-203. https://doi.org/10.1109/SIPS.2005.1579864

    A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction. / Fikos, G.; Nalpantidis, Lazaros; Siskos, S.

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Bind 2005 2005. s. 199-203.

    Publikation: Bidrag til bog/antologi/rapport/konference proceedingBidrag til bog/antologiForskningpeer review

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    AU - Fikos, G.

    AU - Nalpantidis, Lazaros

    AU - Siskos, S.

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    Y1 - 2005/1/1

    KW - Capacitors; CMOS integrated circuits; Noise abatement; Photoelectric cells; Control gate capacitors; Fixed Pattern Noise (FPN); Floating-gate mosfets (FGMOS); Logarithmic response photoarrays; MOS devices

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    Fikos G, Nalpantidis L, Siskos S. A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction. I IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Bind 2005. 2005. s. 199-203 https://doi.org/10.1109/SIPS.2005.1579864