A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

G. Fikos; Lazaros Nalpantidis; S. Siskos

doi:10.1109/SIPS.2005.1579864

A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

G. Fikos, Lazaros Nalpantidis, S. Siskos

Publikation: Bidrag til bog/antologi/rapport/konference proceeding › Bidrag til bog/antologi › Forskning › peer review

1 Citationer (Scopus)

Abstract

A logarithmic response photoarray, incorporating two minimum-sized floating-gate mosfets (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for Fixed Pattern Noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32×32 prototype array implemented in AMS 0.6μm CMOS technology, are presented and discussed.

Originalsprog	Engelsk
Titel	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Antal sider	5
Vol/bind	2005
Publikationsdato	1 jan. 2005
Sider	199-203
ISBN (Trykt)	0780393341, 978-078039334-9
DOI	https://doi.org/10.1109/SIPS.2005.1579864
Status	Udgivet - 1 jan. 2005

Emneord

Capacitors; CMOS integrated circuits; Noise abatement; Photoelectric cells; Control gate capacitors; Fixed Pattern Noise (FPN); Floating-gate mosfets (FGMOS); Logarithmic response photoarrays; MOS devices

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10.1109/SIPS.2005.1579864

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AB - A logarithmic response photoarray, incorporating two minimum-sized floating-gate mosfets (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for Fixed Pattern Noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32×32 prototype array implemented in AMS 0.6μm CMOS technology, are presented and discussed.

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A 32×32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

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