A class of high-input low-output voltage single-step converters with low voltage stress on the primary-side switches and high output current capacity

Huai Wang*, Henry Shu Hung Chung, Adrian Ioinovici


Publikation: Bidrag til tidsskriftTidsskriftartikelForskningpeer review

25 Citationer (Scopus)


Power conversion from an input voltage of several kilovolts to a low load voltage is of great significance in various applications, but poses serious challenges. In this paper, a new converter, which is able to realize such a large step-down conversion in a single step, is proposed by introducing a novel concept of dc-dc multiphase conversion and n-phase interleaving rectification. The proposed structure is formed by n switch pairs in the primary side, an n-phase isolation transformer with the primary windings connected to dc blocking capacitors, and an n-phase current multiplier in the output side. The switching patterns applied to the switch pairs have a phase difference of 360°/n, and the output inductor currents are interleaved correspondingly, making necessary a smaller output filter. For a Vi input voltage and Io load current, the converter features Vi/n voltage stress on the primary-side switches, and Io/n current stress on the secondary-side inductors and diodes. Thus, the magnetic size of the inductors is considerable reduced. The primary-side switches are commutated with zero-voltage-switching (ZVS). Therefore, rather than using insulated-gate bipolar transistors (IGBTs) or MOSFETs with higher voltage ratings, the most available, notable performing 500/600 V MOSFETs can be used in the proposed converter with several kilovolts supply voltage, allowing for a higher operation frequency and lower conduction losses. Compared with an input-series-output-parallel (ISOP) connection of full-bridge (FB) isolated converters, for the same voltage stress on the switches, the proposed converter requires half of the number of transistors and inherently balances the input voltage among the switch pairs. The switching mechanism of a typical switch pair in the kth interval Ts/n of a switching cycle is analyzed. A dc analysis was carried out to determine the dc conversion ratio and the ZVS conditions in an analytical form. It allows for a tradeoff design of the converter, such that to minimize the duty-cycle loss and maximize the ZVS load range. A 1500/48-V, 2-kW prototype with four switch pairs was designed, implemented, and evaluated. The experimental results prove the soft switching of the switches, the low voltage stress across the primary-side switches, and the low current flowing through the rectifiers diodes and inductors. The efficiency measured at nominal power rating was 90.75.
TidsskriftIEEE Transactions on Power Electronics
Udgave nummer6
Sider (fra-til)1659-1672
Antal sider14
StatusUdgivet - 3 aug. 2011
Udgivet eksterntJa

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