A DC-link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter with Single Delta Bridge Cells (MMCC-SDBC)

Takaaki Tanaka, Huai Wang, Frede Blaabjerg

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Resumé

This paper proposes a capacitor voltage ripple reduction method used for a Modular Multilevel Cascade Converter (MMCC) with Single Delta Bridge Cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/ 33 kV MMCC-SDBC based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electro-thermal stresses on IGBT modules are analyzed. An optimal parameter of the current level is obtained by compromising the above performance factors. The obtained result shows that the required capacitance, as well as capacitor bank volume, are reduced by 20 % without increasing the total power semiconductor losses by using the proposed method.
OriginalsprogEngelsk
TidsskriftIEEE Transactions on Industry Applications
ISSN0093-9994
DOI
StatusAccepteret/In press - 2019

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Capacitors
Electric potential
Insulated gate bipolar transistors (IGBT)
Thermal stress
Capacitance
Semiconductor materials
Static synchronous compensators

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title = "A DC-link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter with Single Delta Bridge Cells (MMCC-SDBC)",
abstract = "This paper proposes a capacitor voltage ripple reduction method used for a Modular Multilevel Cascade Converter (MMCC) with Single Delta Bridge Cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/ 33 kV MMCC-SDBC based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electro-thermal stresses on IGBT modules are analyzed. An optimal parameter of the current level is obtained by compromising the above performance factors. The obtained result shows that the required capacitance, as well as capacitor bank volume, are reduced by 20 {\%} without increasing the total power semiconductor losses by using the proposed method.",
author = "Takaaki Tanaka and Huai Wang and Frede Blaabjerg",
year = "2019",
doi = "10.1109/TIA.2019.2934024",
language = "English",
journal = "I E E E Transactions on Industry Applications",
issn = "0093-9994",
publisher = "IEEE",

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TY - JOUR

T1 - A DC-link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter with Single Delta Bridge Cells (MMCC-SDBC)

AU - Tanaka, Takaaki

AU - Wang, Huai

AU - Blaabjerg, Frede

PY - 2019

Y1 - 2019

N2 - This paper proposes a capacitor voltage ripple reduction method used for a Modular Multilevel Cascade Converter (MMCC) with Single Delta Bridge Cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/ 33 kV MMCC-SDBC based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electro-thermal stresses on IGBT modules are analyzed. An optimal parameter of the current level is obtained by compromising the above performance factors. The obtained result shows that the required capacitance, as well as capacitor bank volume, are reduced by 20 % without increasing the total power semiconductor losses by using the proposed method.

AB - This paper proposes a capacitor voltage ripple reduction method used for a Modular Multilevel Cascade Converter (MMCC) with Single Delta Bridge Cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/ 33 kV MMCC-SDBC based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electro-thermal stresses on IGBT modules are analyzed. An optimal parameter of the current level is obtained by compromising the above performance factors. The obtained result shows that the required capacitance, as well as capacitor bank volume, are reduced by 20 % without increasing the total power semiconductor losses by using the proposed method.

U2 - 10.1109/TIA.2019.2934024

DO - 10.1109/TIA.2019.2934024

M3 - Journal article

JO - I E E E Transactions on Industry Applications

JF - I E E E Transactions on Industry Applications

SN - 0093-9994

ER -