An improved design of virtual output impedance loop for droop-controlled parallel three-phase Voltage Source Inverters

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Abstrakt

The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method.
OriginalsprogEngelsk
TitelProceedings of the IEEE Energy Conversion Congress and Exposition 2012
UdgivelsesstedRaleigh, NC
ForlagIEEE Press
Publikationsdato2012
Sider2466-2473
ISBN (Trykt)978-1-4673-0802-1
ISBN (Elektronisk)978-1-4673-0801-4
DOI
StatusUdgivet - 2012
Begivenhedthe Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012 - Raleigh Convention Center, Raleigh, USA
Varighed: 15 sep. 201220 sep. 2012

Konference

Konferencethe Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012
LokationRaleigh Convention Center
LandUSA
ByRaleigh
Periode15/09/201220/09/2012

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