The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method.
|Titel||Proceedings of the IEEE Energy Conversion Congress and Exposition 2012|
|Status||Udgivet - 2012|
|Begivenhed||the Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012 - Raleigh Convention Center, Raleigh, USA|
Varighed: 15 sep. 2012 → 20 sep. 2012
|Konference||the Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012|
|Lokation||Raleigh Convention Center|
|Periode||15/09/2012 → 20/09/2012|