An Improved Seven-Level PUC Inverter Topology With Voltage Boosting

M. Jagabar Sathik, Kaustubh Bhatnagar, N Sandeep, Frede Blaabjerg

Publikation: Bidrag til tidsskriftTidsskriftartikelForskningpeer review

27 Citationer (Scopus)


In this brief, a seven-level (7L) improved packed U-cell (IPUC) inverter with reduced power electronic components is proposed. The presented IPUC inverter has low voltage stress on switches and is capable of voltage boosting. A new voltage balancing method based on logic form equations is developed for regulating the inherent floating capacitor voltage to half the input dc voltage. The proposed 7L IPUC is compared with other state-of-the-art 7L inverters in terms of number of IGBTs, blocking voltage, and driver circuits for attesting its superior merits. The performance of the proposed voltage balancing is verified through a laboratory prototyped 7L IPUC inverter considering varying load conditions and the corresponding results are elucidated.
TidsskriftI E E E Transactions on Circuits and Systems. Part 2: Express Briefs
Udgave nummer1
Sider (fra-til)127-131
Antal sider5
StatusUdgivet - jan. 2020


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