Analysis and Mitigation Methods of Gate Oscillation in Paralleled 10 kV SiC MOSFETs

Gate oscillations exist in paralleled SiC MOSFETs, which can cause false switching behavior and device damage. This article investigates gate oscillations in paralleled 10 kV SiC mosfets as it is currently one of the bottlenecks for paralleling. During the switching transient, the paralleled SiC mosfets operate in their saturation region, where a closed-loop feedback system is formed between the mosfet transconductance and the parasitic distributions in the circuit. The instability of the closed-loop feedback system is key in describing the gate oscillation mechanism. Therefore, a small signal circuit model of two parallel 10 kV SiC mosfets is used to analyze this mechanism, which takes into account both the parasitic inductances and capacitances of the mosfet, power module, and external connections to predict the impact of different parasitic parameters. From the circuit model, four methods are proposed to mitigate the gate oscillations. Finally, experiments are conducted in a double pulse test platform at 6 kV/20 A, showing a good prediction of the gate oscillations and significant damping by the proposed methods.