Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring

Mohammad El-Sayed; Peter Koch; Yannick Le Moullec

doi:10.1109/NORCHIP.2015.7364369

Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring

Mohammad El-Sayed, Peter Koch, Yannick Le Moullec

Institut for Elektroniske Systemer

Publikation: Bidrag til bog/antologi/rapport/konference proceeding › Konferenceartikel i proceeding › Forskning › peer review

1 Citationer (Scopus)

Abstract

We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.

Originalsprog	Engelsk
Titel	Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
Antal sider	5
Forlag	IEEE Press
Publikationsdato	2015
Sider	1-5
ISBN (Elektronisk)	978-1-4673-6576-5
DOI	https://doi.org/10.1109/NORCHIP.2015.7364369
Status	Udgivet - 2015
Begivenhed	Nordic Circuits and Systems Conference (NORCAS) - Oslo, Norge Varighed: 26 okt. 2015 → 28 okt. 2015

Konference

Konference	Nordic Circuits and Systems Conference (NORCAS)
Lokation	Oslo
Land/Område	Norge
Periode	26/10/2015 → 28/10/2015

Adgang til dokumentet

10.1109/NORCHIP.2015.7364369

AUB Link

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Citationsformater

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title = "Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring",

abstract = "We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.",

author = "Mohammad El-Sayed and Peter Koch and {Le Moullec}, Yannick",

year = "2015",

doi = "10.1109/NORCHIP.2015.7364369",

language = "English",

pages = "1--5",

booktitle = "Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015",

publisher = "IEEE Press",

note = "Nordic Circuits and Systems Conference (NORCAS) ; Conference date: 26-10-2015 Through 28-10-2015",

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El-Sayed, M, Koch, P & Le Moullec, Y 2015, Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring. i Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE Press, s. 1-5, Nordic Circuits and Systems Conference (NORCAS), Norge, 26/10/2015. https://doi.org/10.1109/NORCHIP.2015.7364369

Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring. / El-Sayed, Mohammad; Koch, Peter; Le Moullec, Yannick.
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE Press, 2015. s. 1-5.

Publikation: Bidrag til bog/antologi/rapport/konference proceeding › Konferenceartikel i proceeding › Forskning › peer review

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AB - We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.

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