Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Pawel Piotr Kubulus; Szymon Michal Beczkowski; Stig Munk-Nielsen; Asger Bjørn Jørgensen

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Pawel Piotr Kubulus^*, Szymon Michal Beczkowski, Stig Munk-Nielsen, Asger Bjørn Jørgensen

^*Kontaktforfatter

Publikation: Bidrag til bog/antologi/rapport/konference proceeding › Konferenceartikel i proceeding › Forskning › peer review

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Abstract

In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

Originalsprog	Engelsk
Titel	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)
Antal sider	9
Forlag	IEEE (Institute of Electrical and Electronics Engineers)
Publikationsdato	okt. 2022
ISBN (Elektronisk)	9789075815399
Status	Udgivet - okt. 2022
Begivenhed	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) - Hanover, Germany, Hanover, Tyskland Varighed: 5 sep. 2022 → 9 sep. 2022

Konference

Konference	2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)
Lokation	Hanover, Germany
Land/Område	Tyskland
By	Hanover
Periode	05/09/2022 → 09/09/2022

Adgang til dokumentet

0379-epe2022-full-15341524Accepteret manuskript, 2,72 MB

https://ieeexplore.ieee.org/document/9907388

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1 Afsluttet
1 Igangværende

CoDE: Center of Digitalized Electronics (CoDE)
Munk-Nielsen, S. (PI (principal investigator)), Jørgensen, A. B. (CoPI), Uhrenfeldt, C. (CoPI), Beczkowski, S. (Projektdeltager), Ahmad, F. (Projektdeltager), Meinert, J. D. (Projektdeltager), Kubulus, P. P. (Projektdeltager), Takahashi, M. (Projektdeltager), Sun, Z. (Projektdeltager), Wang, R. (Projektdeltager), Gao, Y. (Projektdeltager), Zäch, M. R. (Projektdeltager), Meyer, S. (Projektdeltager), Liccardi, S. (Projektdeltager), Kristensen, N. H. (Projektdeltager) & Steffensen, B. (Projektkoordinator)
Poul Due Jensens Fond
01/01/2021 → 31/12/2026
Projekter: Projekt › Forskning
Digital Twin Based Automated Design for Converters Incorporating Wide-Band Gap Devices
Kubulus, P. P. (PI (principal investigator)), Munk-Nielsen, S. (Supervisor) & Jørgensen, A. B. (Supervisor)
01/09/2021 → 31/08/2024
Projekter: Projekt › Ph.d.-projekt

Citationsformater

Kubulus, P. P., Beczkowski, S. M., Munk-Nielsen, S., & Jørgensen, A. B. (2022). Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. I 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) IEEE (Institute of Electrical and Electronics Engineers). https://ieeexplore.ieee.org/document/9907388

@inproceedings{f82df5d8449a4880bf04c9035ae17b08,

title = "Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment",

abstract = "In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.",

keywords = "Design optimization, MOSFET, Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>",

author = "Kubulus, {Pawel Piotr} and Beczkowski, {Szymon Michal} and Stig Munk-Nielsen and J{\o}rgensen, {Asger Bj{\o}rn}",

year = "2022",

month = oct,

language = "English",

booktitle = "2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)",

publisher = "IEEE (Institute of Electrical and Electronics Engineers)",

address = "United States",

note = "2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe) ; Conference date: 05-09-2022 Through 09-09-2022",

}

Kubulus, PP , Beczkowski, SM , Munk-Nielsen, S & Jørgensen, AB 2022, Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. i 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe). IEEE (Institute of Electrical and Electronics Engineers), 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe), Hanover, Tyskland, 05/09/2022. <https://ieeexplore.ieee.org/document/9907388>

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment. / Kubulus, Pawel Piotr ; Beczkowski, Szymon Michal ; Munk-Nielsen, Stig et al.
2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe). IEEE (Institute of Electrical and Electronics Engineers), 2022.

Publikation: Bidrag til bog/antologi/rapport/konference proceeding › Konferenceartikel i proceeding › Forskning › peer review

TY - GEN

T1 - Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

AU - Kubulus, Pawel Piotr

AU - Beczkowski, Szymon Michal

AU - Munk-Nielsen, Stig

AU - Jørgensen, Asger Bjørn

PY - 2022/10

Y1 - 2022/10

N2 - In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

AB - In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

KW - Design optimization

KW - MOSFET

KW - Parasitic elements Silicon Carbide (SiC> Virtual prototyping >>

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M3 - Article in proceeding

BT - 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)

PB - IEEE (Institute of Electrical and Electronics Engineers)

T2 - 2022 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe)

Y2 - 5 September 2022 through 9 September 2022

ER -

Automated gate impedance network design for SiC MOSFETs using SPICE solver interfaced with MATLAB environment

Abstract

Konference

Adgang til dokumentet

AUB Link

Andre filer og links

Fingeraftryk

Projekter

CoDE: Center of Digitalized Electronics (CoDE)

Digital Twin Based Automated Design for Converters Incorporating Wide-Band Gap Devices

Citationsformater