Projekter pr. år
Abstract
Voltage unbalance and short circuits in distribution networks adversely affect the performance of grid-tied voltage source inverters (VSIs). Consequently, the dc-link voltage ripple may significantly increase leading to operation of VSI in an unsatisfactory manner. Conventionally in order to maintain the negative sequence current under unbalanced conditions, low-pass/trap filter in the current control loop are required which significantly reduce the controller bandwidth. In order to minimize the dc-link voltage ripple without impairing the controller bandwidth, this paper investigates the design and performance of Proportional-Integral-Resonant (PIR) controller in improving the performance of the VSI under unbalanced condition. The proposed design methodology is validated through simulations and experimental results.
Originalsprog | Engelsk |
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Titel | Proceedings of the 19th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2018) |
Antal sider | 8 |
Forlag | IEEE Press |
Publikationsdato | jun. 2018 |
Sider | 1-8 |
Artikelnummer | 8460151 |
ISBN (Trykt) | 978-1-5386-5542-9 |
ISBN (Elektronisk) | 978-1-5386-5541-2 |
DOI | |
Status | Udgivet - jun. 2018 |
Begivenhed | 19th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2018 - Padova, Italien Varighed: 25 jun. 2018 → 28 jun. 2018 |
Konference
Konference | 19th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2018 |
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Land/Område | Italien |
By | Padova |
Periode | 25/06/2018 → 28/06/2018 |
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