Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile architecture. For thermal analysis of our energy efficient design, we have taken temperatures of four different regions from reference. Latin Unicode reader takes 16-bit hexadecimal code of alphabet and clock input. At the end we can conclude that the maximum power consumption is at 2.2GHz and minimum power consumption is at 1.2GHz. When we talk in terms of temperature we can see that maximum power is consumed at 329.85K and minimum power is consumed at 294.15K. And also the power dissipation is less in the case of 40nm (Artix-6) and is more in the case of 28nm (Kintex-7). Changing the parameter (Temperature) doesn’t affect the clock power in both cases (Gated and Non-gated).