Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model

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Software Defined Radio (SDR) devices are becoming
increasingly popular due to their support for mode-, standardand
application-flexibility. At the same time however, the energy
consumption of such devices typically suffers from the use of
reconfigurable real-time platforms which are known to be severely
power hungry. In this work we therefore show how to use tools
and techniques developed by the formal methods community to
minimize the energy consumption of Finite Impulse Response
(FIR) filters which are extensively used in SDR front-ends. We
conduct experiments with four different FIR filter structures
where we initially derive data flow graphs and precedence graphs
using the Synchronous Data Flow (SDF) notation. Based on actual
measurements on the Altera Cyclone IV FPGA, we derive power
and timing estimates for addition and multiplication, including
idling power consumption. We next model the FIR structures
in UPPAAL CORA and employ model checking to find energyoptimal
solutions in linearly priced timed automata. In conclusion
we state that there are significant energy-versus-time differences
between the four structures when we experiment with varying
numbers of adders and multipliers. Similarly, we find that idle
power becomes an important parameter when a high number of
functional units are allocated.
Titel2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Antal sider6
Publikationsdato20 apr. 2016
ISBN (Elektronisk)978-1-5090-2466-7
StatusUdgivet - 20 apr. 2016
BegivenhedInternational Symposium on Design and Diagnostics of Electronic Circuits & Systems - Košice, Slovakiet
Varighed: 20 apr. 201622 apr. 2016


KonferenceInternational Symposium on Design and Diagnostics of Electronic Circuits & Systems


  • FIR Filter
  • FPGA
  • Timed automata
  • VHDL
  • Power Consumption