Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature

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Resumé

This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.
OriginalsprogEngelsk
TitelProceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Antal sider5
Vol/bind2018-July
ForlagIEEE Press
Publikationsdatojul. 2018
Sider1-5
Artikelnummer8452575
ISBN (Trykt)978-1-5386-4930-5
ISBN (Elektronisk)978-1-5386-4929-9
DOI
StatusUdgivet - jul. 2018
Begivenhed25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018 - Singapore, Singapore
Varighed: 16 jul. 201819 jul. 2018

Konference

Konference25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018
LandSingapore
BySingapore
Periode16/07/201819/07/2018
SponsorHamamatsu Photonics K.K., Thermo Fisher Scientific

Fingeraftryk

Short circuit currents
Failure analysis
Electric potential
Temperature
Focused ion beams
Leakage currents
Semiconductor materials
Cracks
Aluminum
Degradation
Silicon
Monitoring

Emneord

    Citer dette

    Reigosa, P. D., Iannuzzo, F., & Ceccarelli, L. (2018). Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. I Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Bind 2018-July, s. 1-5). [8452575] IEEE Press. https://doi.org/10.1109/IPFA.2018.8452575
    Reigosa, Paula Diaz ; Iannuzzo, Francesco ; Ceccarelli, Lorenzo. / Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Bind 2018-July IEEE Press, 2018. s. 1-5
    @inproceedings{8addd53c21304ba5a429b17512c7784b,
    title = "Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature",
    abstract = "This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.",
    keywords = "Logic gates, Silicon carbide, MOSFET, Failure analysis, Leakage currents, Ion beams, Aluminum",
    author = "Reigosa, {Paula Diaz} and Francesco Iannuzzo and Lorenzo Ceccarelli",
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    Reigosa, PD, Iannuzzo, F & Ceccarelli, L 2018, Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. i Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. bind 2018-July, 8452575, IEEE Press, s. 1-5, Singapore, Singapore, 16/07/2018. https://doi.org/10.1109/IPFA.2018.8452575

    Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. / Reigosa, Paula Diaz; Iannuzzo, Francesco; Ceccarelli, Lorenzo.

    Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Bind 2018-July IEEE Press, 2018. s. 1-5 8452575.

    Publikation: Bidrag til bog/antologi/rapport/konference proceedingKonferenceartikel i proceedingForskningpeer review

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    N2 - This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

    AB - This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

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    Reigosa PD, Iannuzzo F, Ceccarelli L. Failure analysis of a degraded 1.2 kV SiC MOSFET after short circuit at high temperature. I Proceedings of the IPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Bind 2018-July. IEEE Press. 2018. s. 1-5. 8452575 https://doi.org/10.1109/IPFA.2018.8452575