Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations

Saeed Golestan, Josep M. Guerrero, Gevork B. Gharehpetian

Publikation: Bidrag til tidsskriftTidsskriftartikelForskningpeer review

76 Citationer (Scopus)
1325 Downloads (Pure)

Abstrakt

The presence of the dc component in the phaselocked loop (PLL) input results in fundamental frequency oscillations in the phase and frequency estimated by the PLL. The removal of these oscillations is a challenging task because of their low frequency. The aim of this paper is to provide a detailed analysis of several approaches that little work has been conducted on their application for addressing the problem of dc offset in the PLL algorithms. These approaches include using the dq-frame delayed signal cancellation (DSC) operator and the notch filter as the PLL in-loop filtering stages, and using the -frame DSC operator, the complex coefficient filter, and a cross-feedback network for blocking the dc offset before the PLL input. Design aspects of these methods are presented, some methods to enhance their performances are proposed, and their advantages and disadvantages are evaluated.
OriginalsprogEngelsk
TidsskriftI E E E Transactions on Power Electronics
Vol/bind31
Udgave nummer1
Sider (fra-til)648 - 661
Antal sider14
ISSN0885-8993
DOI
StatusUdgivet - jan. 2016

Fingeraftryk Dyk ned i forskningsemnerne om 'Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations'. Sammen danner de et unikt fingeraftryk.

Citationsformater