FPGA Based Low Power ROM Design Using Capacitance Scaling

Meenakshi Bansal, Neha Bansal, Rishita Saini, Lakshay Kalra, Preet Mohan Singh, Bishwajeet Pandey, Dil Muhammad Akbar Hussain

Publikation: Bidrag til tidsskriftKonferenceartikel i tidsskriftForskningpeer review

Abstract

An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.
OriginalsprogEngelsk
TidsskriftAdvanced Materials Research
Vol/bind1082
Sider (fra-til)471-474
Antal sider4
ISSN1022-6680
DOI
StatusUdgivet - 2015
Begivenhed4th International Conference on Advanced Materials and Engineering Materials, ICAMEM 2014 - Hong Kong, Hong Kong
Varighed: 19 okt. 201420 okt. 2014

Konference

Konference4th International Conference on Advanced Materials and Engineering Materials, ICAMEM 2014
Land/OmrådeHong Kong
ByHong Kong
Periode19/10/201420/10/2014

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