Impacts of Parasitic Power Loop Inductance on 10 kV SiC MOSFETs

The state-of-the-art research reports large parasitic inductance in the power loop can cause severe overshoot voltages in low voltage silicon-carbide MOSFET converters due to the high di/dt. On the contrary, the parasitic capacitance is significantly stressed in the research for medium voltage applications based on 10 kV silicon-carbide MOSFETs. The parasitic inductance is known from low voltage silicon-carbide MOSFETs to cause switching ringings and oscillations in both gate and power loops, which emphasizes the necessity to quantify its impact on the emerging 10 kV silicon-carbide MOSFETs. This paper experimentally investigates the impacts of the parasitic power loop inductance in a medium voltage power module enabled by 10 kV silicon-carbide MOSFETs. The test results reveal that compared with the low voltage silicon-carbide MOSFETs, the inductance on the drain side has little influence on the 10 kV silicon-carbide MOSFETs. Differently, the source inductance causes gate oscillation in paralleled 10 kV silicon-carbide MOSFETs, which is similar to the low voltage silicon-carbide MOSFETs.