Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

Bishwajeet Pandey, M. Atiqur Rehman, Dil muhammed Akbar Hussain, Abhay Saxena, Bhagwan Das

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1 Citationer (Scopus)
333 Downloads (Pure)

Abstract

The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times total power dissipation. HSTL_I_12, SSTL18_I and LVCMOS12 are the most energy efficient IO standards in HSTL, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA but there is no switching activity. Design static power dissipation of 8-bit Vedic multiplier is almost double of design static power dissipation of 4-bit Vedic multiplier. Device static (leakage) power dissipation of 8-bit Vedic multiplier is almost equal to device static power dissipation of 4-bit Vedic multiplier on 40nm FPGA.
OriginalsprogEngelsk
TidsskriftIndian Journal of Science and Technology
Vol/bind9
Udgave nummer25
Antal sider12
DOI
StatusUdgivet - jul. 2016
BegivenhedInternational Conference on Green Computing and Engineering Technologies 2016 - Esbjerg, Danmark
Varighed: 18 aug. 201620 aug. 2016
http://icgcet.org/prev-conf.html

Konference

KonferenceInternational Conference on Green Computing and Engineering Technologies 2016
Land/OmrådeDanmark
ByEsbjerg
Periode18/08/201620/08/2016
Internetadresse

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