Modeling and Design Guidelines for P⁺ Guard Rings in Lightly Doped CMOS Substrates

Publikation: Bidrag til tidsskriftTidsskriftartikelForskningpeer review

14 Citationer (Scopus)
1455 Downloads (Pure)

Abstrakt

This paper presents a compact model for P+ guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance of P+ guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18- μm CMOS process. In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance
OriginalsprogEngelsk
TidsskriftI E E E Transactions on Electron Devices
Vol/bind60
Udgave nummer9
Sider (fra-til)2854-2861
Antal sider8
ISSN0018-9383
DOI
StatusUdgivet - aug. 2013

Fingeraftryk

Dyk ned i forskningsemnerne om 'Modeling and Design Guidelines for P⁺ Guard Rings in Lightly Doped CMOS Substrates'. Sammen danner de et unikt fingeraftryk.

Citationsformater