Modulation for the AVC-HERIC Inverter to Compensate for Deadtime and Minimum Pulse Width Limitation Distortions

Z. Tang, Y. Yang, M. Su, T. Jiang, F. Blaabjerg, H. Dan, Xiao Liang

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1 Citationer (Scopus)
31 Downloads (Pure)


With the superiority in leakage current suppression, the Active Voltage Clamping Highly Efficient and Reliable Inverter Concept (AVC-HERIC) has become a promising candidate in low- and medium-power PV systems. Additionally, the good power density and low system costs have been attained in the AVC-HERIC due to the removal of the isolation transformers. However, to maintain high efficiency and good power quality under reactive power injection, prior-art modulation methods for the AVC-HERIC should be modified. In this paper, a simple modulation scheme is proposed for the AVC-HERIC, which ensures a bidirectional current path at any time. An improved modulation scheme is implemented according to the reference voltage polarity, and it is integrated into the proposed scheme to enable reactive power injection. Moreover, the improved modulation scheme can maintain the same high efficiency as adopting the unipolar pulse width modulation (UP-PWM) strategy. More importantly, the deadtime and minimum pulse width limitation (MPWL) distortions are compensated effectively by the proposed modulation, leading to a good power quality. Simulations and experimental tests are performed on a 3-kW AVC-HERIC, and the results verify the effectiveness of the proposed modulation.
TidsskriftIEEE Transactions on Power Electronics
Udgave nummer3
Sider (fra-til)2571-2584
Antal sider14
StatusUdgivet - mar. 2020


  • deadtime
  • pulse width modulation (PWM)
  • efficiency
  • power quality
  • reactive power injection
  • minimum pulse width limitation (MPWL)

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