Abstract
Advances in high breakdown voltage SiC MOSFETs is enabling the use of simpler topologies, such as a half-bridge in medium voltage applications. In order to increase the power output it is necessary to parallel multiple MOSFETs, which can be done in power modules. At high voltage operating conditions parasitic capacitances of the power module become increasingly important to consider, due to increased switching losses and increased risk to cause EMI. A 10 kV, 80 A half-bridge design is presented using four MOSFETs in parallel, with a design focus on minimal parasitic capacitances.
Originalsprog | Engelsk |
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Titel | CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems |
Antal sider | 6 |
Forlag | VDE Verlag GMBH |
Publikationsdato | 2020 |
Sider | 154-159 |
ISBN (Elektronisk) | 9783800752263 |
Status | Udgivet - 2020 |
Begivenhed | 11th International Conference on Integrated Power Electronics Systems, CIPS 2020 - Berlin, Tyskland Varighed: 24 mar. 2020 → 26 mar. 2020 |
Konference
Konference | 11th International Conference on Integrated Power Electronics Systems, CIPS 2020 |
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Land/Område | Tyskland |
By | Berlin |
Periode | 24/03/2020 → 26/03/2020 |
Bibliografisk note
Publisher Copyright:© VDE VERLAG GMBH · Berlin · Offenbach.