Output impedance design of parallel-connected UPS inverters

Josep M. Guerrero, Luis García De Vicuña, Jose Matas, Jaume Miret, Miguel Castilla

Publikation: Konferencebidrag uden forlag/tidsskriftPaper uden forlag/tidsskriftForskningpeer review

31 Citationer (Scopus)

Abstrakt

This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner control loops are considered in the design of the controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.
OriginalsprogEngelsk
Publikationsdato1 dec. 2004
Antal sider6
DOI
StatusUdgivet - 1 dec. 2004
Udgivet eksterntJa
Begivenhed2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE -
Varighed: 4 maj 20047 maj 2004

Konference

Konference2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE
Periode04/05/200407/05/2004

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