TY - JOUR
T1 - PaRTAA
T2 - A Real-time Multiprocessor for Mixed-Criticality Airborne Systems
AU - Majumder, Shibarchi
AU - Nielsen, Jens Frederik Dalsgaard
AU - Bak, Thomas
PY - 2020
Y1 - 2020
N2 - Mixed-criticality systems, where multiple systems with varying criticality-levels share a single hardware platform, require isolation between tasks with different criticality-levels. Isolation can be achieved with software-based solutions or can be enforced by a hardware level partitioning. An asymmetric multiprocessor architecture offers hardware-based isolation at the cost of underutilized hardware resources, and the inter-core communication mechanism is often a single point of failure in such architectures. In contrast, a partitioned uniprocessor offers efficient resource utilization at the cost of limited scalability. We propose a partitioned real-time asymmetric architecture (PaRTAA) specifically designed for mixed-criticality airborne systems, featuring robust partitioning within processing elements for establishing isolation between tasks with varying criticality. The granularity in the processing element offers efficient resource utilization where inter-dependent tasks share the same processing element for sequential execution while preserving isolation, and independent tasks simultaneously execute on different processing elements as per system requirements.
AB - Mixed-criticality systems, where multiple systems with varying criticality-levels share a single hardware platform, require isolation between tasks with different criticality-levels. Isolation can be achieved with software-based solutions or can be enforced by a hardware level partitioning. An asymmetric multiprocessor architecture offers hardware-based isolation at the cost of underutilized hardware resources, and the inter-core communication mechanism is often a single point of failure in such architectures. In contrast, a partitioned uniprocessor offers efficient resource utilization at the cost of limited scalability. We propose a partitioned real-time asymmetric architecture (PaRTAA) specifically designed for mixed-criticality airborne systems, featuring robust partitioning within processing elements for establishing isolation between tasks with varying criticality. The granularity in the processing element offers efficient resource utilization where inter-dependent tasks share the same processing element for sequential execution while preserving isolation, and independent tasks simultaneously execute on different processing elements as per system requirements.
KW - Single Core Equivalence
KW - Processor Architecture
KW - Avionics on Multi-core
KW - Mixed-criticality Systems
KW - Integrated Modular Avionics
KW - Robust Resource Partitioning
UR - http://www.scopus.com/inward/record.url?scp=85086718523&partnerID=8YFLogxK
UR - https://www.computer.org/csdl/journal/tc/5555/01/09118979/1kHUM91bby0
U2 - 10.1109/TC.2020.3002697
DO - 10.1109/TC.2020.3002697
M3 - Journal article
SN - 0018-9340
VL - 69
SP - 1221
EP - 1232
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 8
M1 - 9118979
ER -