Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA

Vandana Thind, Bishwajeet Pandey, Dil muhammed Akbar Hussain

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2 Citationer (Scopus)
233 Downloads (Pure)

Abstrakt

In this work, we have done power analysis ofData Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration areclock power, logic power, signals power, IOs power, leakage powerand supply power (dynamic and quiescent). We have used four different WLAN frequencies (2.4 GHz, 3.6 GHz, 4.9GHz, and 5.9 GHz) and four different IO standards like HSTL-I, HSTL-II, HSTL-II-18, HSTL-I-18 for power analysis. We have achieved13-47% saving in power at different frequencies and withdifferent energy efficient HSTL IO standard. We calculated the percentage change in the IO power with respect to the mean values of IO power at four different frequencies. We notified that there is minimum of -37.5% and maximum of +35.8% variations.This work helps to design and implement DES algorithm with maximum power efficiency.
OriginalsprogEngelsk
TitelProceedings of the 15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science (DCABES 2016)
Antal sider4
UdgivelsesstedParis, France
ForlagIEEE Press
Publikationsdatoaug. 2016
Sider600-603
ISBN (Trykt)978-1-5090-3593-9
DOI
StatusUdgivet - aug. 2016
Begivenhed15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science - Paris, Frankrig
Varighed: 24 aug. 201626 aug. 2016
Konferencens nummer: 15
http://dcabes2016.conferences-events.org/

Konference

Konference15th International Symposium on Distributed Computing and Applications to Business, Engineering and Science
Nummer15
LandFrankrig
ByParis
Periode24/08/201626/08/2016
Internetadresse

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