TY - GEN
T1 - Power Density and Loss Optimization Design Methodology of a 10 kW 2-Level 3-Phase SiC Inverter
AU - Nielsen, Alex Buus
AU - Davari, Pooya
AU - Blaabjerg, Frede
AU - Nielsen, Bo Vork
PY - 2020
Y1 - 2020
N2 - In this paper an optimization methodology is developed to design a 10 kW 2-level 3-phase inverter, from a power density, efficiency, and complexity point of view. A numeric iterative SiC MOSFET loss and temperature model is build, for analysing the effect of the switching frequency and the cooling system design, on power handling capability and efficiency, for effectively selecting an appropriate SiC MOSFET. Furthermore, a LC filter inductor design algorithm is used to investigate potential volume and weight reduction for different switching frequencies. Using the semiconductor and inductor design information to do a multi-objective optimization analysis, a switching frequency of 40 kHz is chosen. It is shown that an amorphous core can be smaller and lighter than a KoolMu Max toroidal core, while still achieving a peak efficiency of 98.8%. A prototype converter is built, and the inductor, capacitor and heat sink models are verified within a fairly good deviation below 17 %. The experimental measurements shows good harmonic performance, and no excessive ringing and overshoot either at turn-on or turn-off of the low-side SiC MOSFET's.
AB - In this paper an optimization methodology is developed to design a 10 kW 2-level 3-phase inverter, from a power density, efficiency, and complexity point of view. A numeric iterative SiC MOSFET loss and temperature model is build, for analysing the effect of the switching frequency and the cooling system design, on power handling capability and efficiency, for effectively selecting an appropriate SiC MOSFET. Furthermore, a LC filter inductor design algorithm is used to investigate potential volume and weight reduction for different switching frequencies. Using the semiconductor and inductor design information to do a multi-objective optimization analysis, a switching frequency of 40 kHz is chosen. It is shown that an amorphous core can be smaller and lighter than a KoolMu Max toroidal core, while still achieving a peak efficiency of 98.8%. A prototype converter is built, and the inductor, capacitor and heat sink models are verified within a fairly good deviation below 17 %. The experimental measurements shows good harmonic performance, and no excessive ringing and overshoot either at turn-on or turn-off of the low-side SiC MOSFET's.
U2 - 10.1109/COMPEL49091.2020.9265687
DO - 10.1109/COMPEL49091.2020.9265687
M3 - Article in proceeding
SN - 978-1-7281-7161-6
T3 - IEEE Workshop on Control and Modeling for Power Electronics (COMPEL)
SP - 1
EP - 7
BT - 21th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL) 2020
PB - IEEE
T2 - 21th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2020
Y2 - 9 November 2020 through 12 November 2020
ER -