Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

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6 Citationer (Scopus)
17 Downloads (Pure)

Resumé

The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.
OriginalsprogEngelsk
TitelProceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Antal sider8
Udgivelses stedWarsaw, Poland
ForlagIEEE Press
Publikationsdatosep. 2017
ISBN (Elektronisk)978-90-75815-27-6
DOI
StatusUdgivet - sep. 2017
Begivenhed2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Polen
Varighed: 11 sep. 201714 sep. 2017

Konference

Konference2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
LandPolen
ByWarsaw
Periode11/09/201714/09/2017

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Heat sinks
Silicon carbide
Capacitance
Finite element method
Signal interference
Semiconductor materials
Networks (circuits)
Power MOSFET
Wide band gap semiconductors

Emneord

    Citer dette

    Jørgensen, A. B., Christensen, N., Dalal, D. N., Sønderskov, S. D., Beczkowski, S., Uhrenfeldt, C., & Munk-Nielsen, S. (2017). Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. I Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) Warsaw, Poland: IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962
    Jørgensen, Asger Bjørn ; Christensen, Nicklas ; Dalal, Dipen Narendrabhai ; Sønderskov, Simon Dyhr ; Beczkowski, Szymon ; Uhrenfeldt, Christian ; Munk-Nielsen, Stig. / Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). Warsaw, Poland : IEEE Press, 2017.
    @inproceedings{79b1a0093a2e4e2992c3158a0369349d,
    title = "Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM",
    abstract = "The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.",
    keywords = "Packaging, Simulation, Wide bandgap devices, Silicon carbide (SiC)",
    author = "J{\o}rgensen, {Asger Bj{\o}rn} and Nicklas Christensen and Dalal, {Dipen Narendrabhai} and S{\o}nderskov, {Simon Dyhr} and Szymon Beczkowski and Christian Uhrenfeldt and Stig Munk-Nielsen",
    year = "2017",
    month = "9",
    doi = "10.23919/EPE17ECCEEurope.2017.8098962",
    language = "English",
    booktitle = "Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)",
    publisher = "IEEE Press",

    }

    Jørgensen, AB, Christensen, N, Dalal, DN, Sønderskov, SD, Beczkowski, S, Uhrenfeldt, C & Munk-Nielsen, S 2017, Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. i Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press, Warsaw, Poland, Warsaw, Polen, 11/09/2017. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962

    Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. / Jørgensen, Asger Bjørn; Christensen, Nicklas; Dalal, Dipen Narendrabhai; Sønderskov, Simon Dyhr; Beczkowski, Szymon; Uhrenfeldt, Christian; Munk-Nielsen, Stig.

    Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). Warsaw, Poland : IEEE Press, 2017.

    Publikation: Bidrag til bog/antologi/rapport/konference proceedingKonferenceartikel i proceedingForskningpeer review

    TY - GEN

    T1 - Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

    AU - Jørgensen, Asger Bjørn

    AU - Christensen, Nicklas

    AU - Dalal, Dipen Narendrabhai

    AU - Sønderskov, Simon Dyhr

    AU - Beczkowski, Szymon

    AU - Uhrenfeldt, Christian

    AU - Munk-Nielsen, Stig

    PY - 2017/9

    Y1 - 2017/9

    N2 - The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

    AB - The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

    KW - Packaging

    KW - Simulation

    KW - Wide bandgap devices

    KW - Silicon carbide (SiC)

    U2 - 10.23919/EPE17ECCEEurope.2017.8098962

    DO - 10.23919/EPE17ECCEEurope.2017.8098962

    M3 - Article in proceeding

    BT - Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)

    PB - IEEE Press

    CY - Warsaw, Poland

    ER -

    Jørgensen AB, Christensen N, Dalal DN, Sønderskov SD, Beczkowski S, Uhrenfeldt C et al. Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. I Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). Warsaw, Poland: IEEE Press. 2017 https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962