Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

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18 Citationer (Scopus)
130 Downloads (Pure)

Abstrakt

The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.
OriginalsprogEngelsk
TitelProceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Antal sider8
Udgivelses stedWarsaw, Poland
ForlagIEEE Press
Publikationsdatosep. 2017
ISBN (Elektronisk)978-90-75815-27-6
DOI
StatusUdgivet - sep. 2017
Begivenhed2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Polen
Varighed: 11 sep. 201714 sep. 2017

Konference

Konference2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
LandPolen
ByWarsaw
Periode11/09/201714/09/2017

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  • Citationsformater

    Jørgensen, A. B., Christensen, N., Dalal, D. N., Sønderskov, S. D., Beczkowski, S., Uhrenfeldt, C., & Munk-Nielsen, S. (2017). Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM. I Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8098962