Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

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7 Citationer (Scopus)

Originalsprog	Engelsk
Tidsskrift	Circuits, Systems, and Signal Processing
ISSN	0278-081X
DOI	https://doi.org/10.1007/s00034-016-0335-2
Status	Udgivet - 2017

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title = "Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA",

author = "Arish Sateesan and R.K. Sharma",

year = "2017",

doi = "10.1007/s00034-016-0335-2",

language = "English",

journal = "Circuits, Systems, and Signal Processing",

issn = "0278-081X",

publisher = "Birkhauser Boston",

}

TY - JOUR

T1 - Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

AU - Sateesan, Arish

AU - Sharma, R.K.

PY - 2017

Y1 - 2017

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-85013005033&partnerID=MN8TOARS

U2 - 10.1007/s00034-016-0335-2

DO - 10.1007/s00034-016-0335-2

M3 - Journal article

SN - 0278-081X

JO - Circuits, Systems, and Signal Processing

JF - Circuits, Systems, and Signal Processing

ER -