Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

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Resumé

Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.
OriginalsprogEngelsk
TitelProceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
Antal sider8
ForlagIEEE Press
Publikationsdatosep. 2017
ISBN (Elektronisk)978-90-75815-27-6
DOI
StatusUdgivet - sep. 2017
Begivenhed2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Polen
Varighed: 11 sep. 201714 sep. 2017

Konference

Konference2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
LandPolen
ByWarsaw
Periode11/09/201714/09/2017

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Transistors
Electric potential
Inductance
Tuning
Wire
Industry

Citer dette

Beczkowski, S., Jørgensen, A. B., Li, H., Uhrenfeldt, C., Dai, X., & Munk-Nielsen, S. (2017). Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs. I Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8099245
Beczkowski, Szymon ; Jørgensen, Asger Bjørn ; Li, Helong ; Uhrenfeldt, Christian ; Dai, Xiaoping ; Munk-Nielsen, Stig. / Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs. Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press, 2017.
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title = "Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs",
abstract = "Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.",
keywords = "Packaging, Power semiconductor device, Silicon carbide (SiC), Parallel operation",
author = "Szymon Beczkowski and J{\o}rgensen, {Asger Bj{\o}rn} and Helong Li and Christian Uhrenfeldt and Xiaoping Dai and Stig Munk-Nielsen",
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Beczkowski, S, Jørgensen, AB, Li, H, Uhrenfeldt, C, Dai, X & Munk-Nielsen, S 2017, Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs. i Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press, Warsaw, Polen, 11/09/2017. https://doi.org/10.23919/EPE17ECCEEurope.2017.8099245

Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs. / Beczkowski, Szymon; Jørgensen, Asger Bjørn; Li, Helong; Uhrenfeldt, Christian; Dai, Xiaoping; Munk-Nielsen, Stig.

Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press, 2017.

Publikation: Bidrag til bog/antologi/rapport/konference proceedingKonferenceartikel i proceedingForskningpeer review

TY - GEN

T1 - Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

AU - Beczkowski, Szymon

AU - Jørgensen, Asger Bjørn

AU - Li, Helong

AU - Uhrenfeldt, Christian

AU - Dai, Xiaoping

AU - Munk-Nielsen, Stig

PY - 2017/9

Y1 - 2017/9

N2 - Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.

AB - Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.

KW - Packaging

KW - Power semiconductor device

KW - Silicon carbide (SiC)

KW - Parallel operation

U2 - 10.23919/EPE17ECCEEurope.2017.8099245

DO - 10.23919/EPE17ECCEEurope.2017.8099245

M3 - Article in proceeding

BT - Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)

PB - IEEE Press

ER -

Beczkowski S, Jørgensen AB, Li H, Uhrenfeldt C, Dai X, Munk-Nielsen S. Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs. I Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE Press. 2017 https://doi.org/10.23919/EPE17ECCEEurope.2017.8099245