Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries. Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on.
|Titel||Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)|
|Status||Udgivet - sep. 2017|
|Begivenhed||2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe) - Warsaw, Polen|
Varighed: 11 sep. 2017 → 14 sep. 2017
|Konference||2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)|
|Periode||11/09/2017 → 14/09/2017|