Abstract
This poster presentation outlines a proposed framework for handling mapping of signal processing
applications to heterogeneous reconfigurable architectures. The methodology consists of an
extension to traditional multi-processor scheduling by creating a separate HW track for generation
of groups of tasks that are handled similarly to SW processes in a traditional multi-processor
scheduling context.
applications to heterogeneous reconfigurable architectures. The methodology consists of an
extension to traditional multi-processor scheduling by creating a separate HW track for generation
of groups of tasks that are handled similarly to SW processes in a traditional multi-processor
scheduling context.
| Originalsprog | Engelsk |
|---|---|
| Publikationsdato | 2008 |
| Status | Udgivet - 2008 |
| Begivenhed | HiPEAC Advanced Computer Architectures and Compilation for Embedded Systems Summer School - L'Aquila, Italien Varighed: 13 jul. 2008 → 19 jul. 2008 Konferencens nummer: 4 |
Konference
| Konference | HiPEAC Advanced Computer Architectures and Compilation for Embedded Systems Summer School |
|---|---|
| Nummer | 4 |
| Land/Område | Italien |
| By | L'Aquila |
| Periode | 13/07/2008 → 19/07/2008 |