TY - JOUR
T1 - Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family
AU - Pandey, Sujeet
AU - Das, Bhagwan
AU - Hussain, Dil muhammed Akbar
PY - 2018/1
Y1 - 2018/1
N2 - This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.
AB - This is an apporach to design of energy efficient traffic light controller on Virtex-7 FPGA that consume low amount of power. There is a reduction of 46.31%, 70.11% and 82.58% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 25oC.There is a reduction of 52.48%, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50oC. There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.
KW - Verilog
KW - FPGA
KW - Energy Efficient design
KW - Traffic Light Controller
U2 - 10.21058/gjet.2018.41004
DO - 10.21058/gjet.2018.41004
M3 - Journal article
SN - 2456-0065
VL - 4
SP - 31
EP - 38
JO - Gyancity Journal of Engineering and Technology
JF - Gyancity Journal of Engineering and Technology
IS - 1
ER -